Posedge Daily
Two hardware interview questions every day, one RTL design and one verification, released at 12:00 AM Eastern. Write SystemVerilog in your browser and run it against hidden tests.
Screenshot
At a glance
- One RTL design question and one verification question each day
- Browser editor with a built-in waveform viewer, no tools to install
- Verilator and Icarus Verilog simulation, with the UVM library available
- Hidden testbenches grade your code, and failed submissions cost nothing
- Streak leaderboard and a discussion forum for every question
Topics
RTL design: state machines, datapath and arithmetic, handshakes and flow control, clocks, resets and CDC, arbiters and memory structures.
Verification: assertions (SVA), constraints and randomization, scoreboards and reference models, processes and synchronization, classes and data structures, and UVM.
How it works
Each day brings new questions. Edit the starting files, run your design to see the log and waveform, then submit to be graded. Every question is worth 100 points on its own day. Answering a past day costs 5 points per day late, down to a minimum of 60, and catch-ups do not extend your streak. Viewing the reference solution before you solve a question halves its points, and after you solve it, it is free. Questions and answers stay on the server until they are released or earned.
Safe by design
Your code runs only inside throwaway sandboxed containers with no network access, strict time and memory limits, and a read-only filesystem.
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